`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/26/2019 05:53:48 PM
// Design Name: 
// Module Name: counter_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module counter_test(
        input CLK,
        input RST,
        output reg CO,
        output reg [5:0] CNT
        );
        
        
        parameter MAX=6'b000101;
        
        
        always @(posedge RST or posedge CLK)
        begin
            if(RST)
            begin
                CNT <= 6'b000000;
                CO <= 0;
            end
            else
            begin
                if(CNT == MAX - 1)
                begin
                    CNT<=6'b000000;
                    CO <= 1;
                end
                else
                begin
                    CNT<=CNT+6'b000001;
                    CO <= 0;
                end
            end
        end

endmodule